1. Field of the Invention
The present invention relates to a timing analysis method and apparatus. More particularly, the present invention relates to a timing analysis method and apparatus for large-scale integrated circuits.
2. Description of the Related Art
Recently, extremely accurate timing analysis has been required in designing recent ultra-high-speed LSIs that operate at clock frequencies exceeding several GHz. Techniques that perform timing analysis based on simulation using the industry standard SPICE have long been known in the art, but such techniques require a very long processing time to finish and, with the ever increasing scale of circuit integration, the situation is reaching the point where it is no longer possible to finish timing analysis in a practical time.
In these techniques, the following method is known for providing an effective solution. First, the circuit to be analyzed is partitioned into small-scale blocks. SPICE simulation is performed on a block-by-block basis, and the results of the simulation are stored in the form of a library. Then, using the library thus created for each block, STA (Static Timing Analysis) of the entire circuit is performed to analyze the timing operations of the LSI circuit.
More specifically, in the prior art, the timing analysis of a large-scale integrated (LSI) circuit has been performed, for example, in the following procedure.
(1) First, from the circuit to be analyzed, a circuit is extracted that has a scale that can be simulated using SPICE, or the circuit is corrected to a scale that can be simulated using SPICE. The circuit extraction (correction) here is done manually or using a tool.
(2) Next, simulation conditions (simulation patterns, etc.) are manually set for the circuit to be analyzed, and the SPICE simulation is carried out.
(3) The above steps (1) and (2) are repeated to complete the timing analysis of the entire circuit.
This technique is effective and makes it possible to accomplish the timing analysis in a practical time. However, in the case of LSI circuits for which feature sizes are decreasing and the packing density increasing year by year, it is not possible, even with the above technique, to provide the necessary accuracy for paths, such as a clock path, that require high accuracy.
In the prior art, Japanese Unexamined Patent Publication (Kokai) No. 10-063693 proposes a delay time calculation method that can calculate delays times at high speed and with high accuracy for large-scale logic circuits; in this method, for every path that requires a high-accuracy calculation, a high-accuracy calculation target path condition library is taken as an input, the path that matches the condition is selected by referring to the path signal delay time obtained by a static delay calculation, and circuit simulation data for the selected path and input signals (test patterns) to the circuit simulation are generated based on the logic circuit connection information for that selected path.
Further, in the prior art, Japanese Unexamined Patent Publication (Kokai) No. 2002-215710 proposes a method wherein, in a full-custom LSI design, even when the circuit design or signal propagation conditions are partially changed, the delay characteristics are analyzed quickly and accurately by using the results of the analysis performed on the original circuit; in this method, the netlist is partitioned into unit blocks, circuit blocks of prescribed scale are formed by combining the unit blocks in accordance with prescribed conditions, dynamic timing analysis is performed on each circuit block to create a delay characteristic library containing the results of the analysis and, by applying the library to static timing analysis, the analysis target circuit described by the netlist is treated as a collection of circuit blocks and the propagation delay along the desired signal path is analyzed.
However, in the above-described prior art timing analysis methods for large-scale integrated circuits, the simulation conditions for the extracted (corrected) circuit differed considerably from the actual circuit operation, giving rise to the problem of poor accuracy. Furthermore, the scale of the extracted circuit tended to become large in order to increase the accuracy, and it took considerable time to complete one SPICE simulation. Further, since the simulation conditions such as simulation patterns had to be set manually, the whole task was very laborious.